The present invention relates generally to network testing. More particularly, the present invention relates to integrated circuits for stress testing a network.
Data networks are becoming increasingly important to all sectors of the economy. As the reliance on these data networks rises, so do the costs of network downtime or even less than optimal network performance. For these reasons, network testing, troubleshooting, and monitoring has also become increasingly important.
One approach to network testing is to purchase and deploy specialized network test equipment to test the network. One disadvantage of this approach is that such equipment is very expensive, especially when capable of testing very fast networks. Another disadvantage is that installing this specialized equipment to obtain meaningful measurements usually requires changing the network topology, possibly interfering with the normal operation of the network.
Another approach is to run network testing applications in existing network devices such as routers and the like that have built-in central processing units (CPUs). One disadvantage of this approach is that the network testing applications burden the CPUs and therefore reduce the performance of such network devices in their normal network roles. Furthermore, these CPUs are limited in performance relative to the number of ports and their speed in the network, and so cannot handle traffic at wirespeed.